1. Field of the Invention
The present invention relates to a dynamic type semiconductor memory device having a sense amplifier for amplifying a micro signal on a bit line and outputting it.
2. Description of the Related Art
A circuit arrangement of a sense amplifier section in a conventional dynamic type semiconductor memory device (to be referred to as a DRAM hereinafter) is shown in FIG. 116, and an operation waveform thereof is shown in FIG. 127.
That is, when a signal of a word line WL rises, a MOS transistor 1 in a memory cell MC is turned on, and a signal corresponding to data stored in a capacitor 2 is read out to the bit line BL, thereby generating a micro potential difference between a pair of bit lines BL and BL. Thereafter, when a signal of a sense amplifier control line SAN for activating an n-channel side sense amplifier consisting of two n-channel MOS transistors 3 and 4 is disabled, a potential of the bit line (BL in FIG. 127) on a low-potential side is continuously decreased. Meanwhile, when a signal of a sense amplifier control line SAP for activating a p-channel side sense amplifier consisting of two p-channel MOS transistors 5 and 6 is raised, a potential of the bit line (BL in FIG. 127) on a high-potential side is continuously increased. When a potential difference between the bit lines BL and BL is sufficiently large, a signal of the column selecting line CSL is raised, and a pair of column selecting n-channel MOS transistors 7 and 8 are turned on. Thus, a bit line signal is generated from a pair of data input/output lines DQ and DQ which is precharged to a predetermined potential.
In the conventional DRAM, however, a signal of the pair of bit lines cannot be transmitted to a pair of data input/output lines at a high speed, because the column selecting line CSL cannot be raised unless a sense amplifier is activated to largely amplify the potential difference between the pair of bit lines. If the column selecting line CSL is raised when the potential difference between the pair of bit lines is small, charges precharged in the pair of data input/output lines flow into the pair of bit lines so that the potentials of the pair of bit lines float, and data may be broken due to unbalance of the potentials of the pair of bit lines. In addition, when an integration density of memory cells in a DRAM is increased, a time required for amplifying the potential difference between the pair of bit lines is further prolonged. Therefore, since a delay time of the sense amplifier section occupies a very large part in an access time, the delay time will be further increased in the future.